The present invention relates to a computer system having a bus bridge for coupling a processor bus and an I/O bus.
The processing speed of recent computers has remarkably increased, to which increases in processing speeds of CPUs, memories, and external/internal buses have contributed.
To reduce the b us traffic of the internal bus, a CPU bus to which the CPU is connected is separated from an I/O bus, e.g., a PCI (Peripheral Component Interconnect) bus, to which various I/O devices, a graphics controller, and the like are connected. In this case, the two buses are connected through a bus bridge.
The bus bridge has an interface with the main memory, in addition to the bus interfaces. The bus bridge is so constructed as to allow either the CPU bus or the I/O bus to access the ma in memory.
FIG. 1 is a block diagram showing the arrangement of a computer system having a bus bridge.
In FIG. 1, reference numeral 1 denotes a CPU; 2, a level 1 cache inside the CPU 1; 3, a level 2 cache; 4, a bus bridge; 5, a main memory; 6, a bus master; 7, a CPU bus (first bus); and 8, an I/O bus (second bus).
In the computer system having a bus bridge, software executed by the CPU 1, and the bus master 6, e.g., a SCSI (Small Computer System Interface) or a network device, which is connected to the I/O bus 8 share data in the main memory 5, and perform processing while exchanging information therebetween.
With this arrangement, the load of the CPU 1 can be reduced, resulting in an improvement in processing performance of the overall system.
The improvement in system performance is greatly influenced by the processing performance of the bus bridge 4.
Particularly, it is important to improve the respective data transfer abilities between the CPU 1 and the main memory 5 and between the bus master 6 and the main memory 5.
The operation of the CPU 1 in the computer system having a bus bridge will be described in brief.
The CPU 1 reads out an instruction and data (operand) required for an operation from the main memory 5, and writes an operation result and the like in the main memory 5.
In the example of FIG. 1, the CPU 1 incorporates the cache 2 therein, and both the caches 2 and 3 are of the write-back scheme.
Except for special cases, an operation of reading out data from the main memory 5 by the CPU 1 is a refill operation with respect to the cache 2 (cache refill operation). The data read operation of the CPU 1 from the main memory 5 is therefore performed by burst transfer in units of the cache line size (e.g., 32-byte data; 64-bit data.times.4 times).
A refill operation with respect to the cache 3 is also executed in parallel to the refill operation with respect to the cache 2.
When the read address from the CPU 1 satisfies a cache hit on the cache 3, data is read out not from the main memory 5 but from the cache 3, and transferred.
In the memory write operation by the CPU 1, when the write address satisfies a cache hit on the cache 3, data is written not in the main memory 5 but only in the cache 3. At this time, data at this address is in the dirty state. When the write address from the CPU 1 does not satisfy a cache hit on the cache 3, the data is written in only the main memory 5.
Next, an access operation of the bus master 6 with respect to the main memory 5 in the computer system having a bus bridge will be explained.
Normally, a plurality of bus masters 6 are connected to the I/O bus 8. Each bus master 6 starts the bus cycle after it gains control of the I/O bus 8 by some means.
For example, when the I/O bus 8 is a PCI bus, one bus arbiter (not shown) exists. This bus arbiter arbitrates request signals output from the respective bus masters 6, and asserts a grant signal to give one bus master 6 the right to use the I/O bus 8.
The bus master 6 which gained control of the bus by the grant signal from this bus arbiter starts the bus cycle on the I/O bus 8. This bus cycle is started by the address of a target to which the bus master 6 wants to access, and a command. The command represents, e.g., whether the bus cycle is a read or write cycle.
In this example, since the bus master 6 accesses the main memory 5, the target is the bus bridge 4, which accesses the main memory 5 instead.
This computer system having a bus bridge has one problem about the data transfer ability between the bus master 6 and the main memory 5.
That is, the data transfer ability is influenced by the cache 2 or 3 which exists in the CPU 1 or on the CPU bus 7.
Of data stored in the main memory 5, the cache 2 or 3 stores data which is frequently used by the CPU 1. When the CPU 1 updates data in the main memory 5, if a cache hit occurs on the cache 2 or 3, only data in the cache 2 or 3 is updated, and data in the main memory 5 is not immediately updated. The computer system employs this scheme called the write-back scheme.
This scheme is subject to a problem when, in accessing the main memory 5 by the bus master 6, the latest data corresponding to the address exists not in the main memory 5 but only in the cache 2 or 3.
In this case, the state of the cache 2 or 3 on the CPU 1 side must be snooped before the bus master 6 accesses the main memory 5.
More specifically, it is snooped to see whether data at an address A which the bus master 6 wants to access exists in the cache 2 or 3. If the data exists, it is snooped to see whether the data is in the updated (dirty) state. If the data is in the dirty state, data at the address A in the cache is invalidated, the data at the address A is written back in the main memory 5, and then the bus master 6 accesses the main memory 5.
The invalidation processing for a cache is an operation commonly required for systems carrying caches thereon, whereas the write-back processing is an operation unique to a cache of the write-back scheme.
The main memory rewrite scheme by a cache includes the write-through scheme and the write-back scheme. In general, the write-back scheme is valuated to have higher performance.
When the bus master 6 accesses the main memory 5, however, the cache of the write-back scheme requires write-back processing as described above. As the frequency of write-back operations increases, i.e., the data sharing rate between the CPU 1 and the bus master 6 increases, the data read/write operation speed of the bus master 6 cannot be increased.
Since the bus master (e.g., a SCSI or a network device) 6 is generally used to realize high-speed data transfer, a decrease in speed of data transfer with the main memory 5 is fatal to the bus master 6. In some cases, the bus master 6 does not correctly operate. To avoid the decrease in data transfer speed, for example, a data buffer having a large capacity must be arranged on the bus master 6 side.
This, however, results in an increase in cost, so this is not a wise practice.
FIG. 2 is a block diagram showing the arrangement of a conventional bus bridge used in the computer system shown in FIG. 1.
In FIG. 2, reference numeral 9 denotes an I/O bus control section; 10, a cache snooping section; 11, a main memory control section; and 12, a write-back control section.
Reference symbol "a" denotes a cache snooping request signal output from the I/O bus control section 9 to the cache snooping section 10; "b", a cache snooping result signal (representing the necessity/unnecessity of write-back processing) output from the cache snooping section 10 to the I/O bus control section 9; "c", a write-back processing request signal output from the cache snooping section 10 to the write-back control section 12; "d", a main memory write-back request signal output from the write-back control section 12 to the main memory control section 11; "e", a main memory write-back end signal output from the main memory control section 11 to the write-back control section 12; "f", a write-back processing end signal output from the write-back control section 12 to the I/O bus control section 9; "g", a main memory access request signal output from the I/O bus control section 9 to the main memory control section 11; and ="h", a main memory access end signal output from the main memory control section 11 to the I/O bus control section 9.
A case wherein processing in response to a read request from a given bus master 6 to the main memory 5 is performed through the conventional bus bridge will be described.
When the bus master 6 gains control of the I/O bus 8, and outputs an address and a read command onto the I/O bus 8, the I/O bus control section 9 of the bus bridge 4 receives the address and the read command to transfer the address to the cache snooping section 10 and outputs a cache snooping request signal "a" thereto.
The cache snooping section 10 outputs the address transferred from the I/O bus control section 9 onto the CPU bus 7, and outputs a cache snooping command. Then, the cache 2 inside the CPU 1, and the cache 3 detect the cache snooping command, and snoop to see whether data corresponding to the address output onto the CPU bus 7 is cached.
The states of the two caches 2 and 3 can be classified into the following five states (1) to (5).
(1) Neither of the caches 2 and 3 have cached the data corresponding to the supplied address (cache miss).
In this case, the states of the caches 2 and 3 do not change and do not influence (write back) the main memory 5. Therefore, a read access to the main memory 5 can be immediately started in response to a request from the bus master 6.
(2) Although one or both of the caches 2 and 3 have cached data corresponding to the supplied address (cache hit), the data has not been updated (not dirty) by the CPU 1.
In this case, since a write-back operation with respect to the main memory 5 is not performed, and the read access request is the one output from the bus master 6, the state (valid or invalid) of the cache does not change. Also in this case, a read access to the main memory 5 can be immediately started in response to a request from the bus master 6.
(3) One or both of the caches 2 and 3 have cached data corresponding to the supplied address, and only the data in the cache 2 has been updated (dirty).
In this case, the data from the cache 2 is first written back in the main memory 5. Then, the data in the cache 2 changes from the "dirty" state to the "clean" state. Upon completion of the write-back operation, a read access to the main memory 5 can be started in response to a request from the bus master 6.
(4) One or both of the caches 2 and 3 have cached data corresponding to the supplied address, and only the data in the cache 3 has been updated (dirty).
In this case, the data from the cache 3 is first written back in the main memory 5. Then, the data in the cache 3 changes from the "dirty" state to the "clean" state. Upon completion of the write-back operation, a read access to the main memory 5 can be started in response to a request from the bus master 6.
(5) One or both of the caches 2 and 3 have cached data at the supplied address, and both the data in the caches 2 and 3 have been updated (dirty).
In this case, the data from the cache 2 is written back in the main memory 5. The data in the cache 3 is replaced with the write-back data. Then, both the data in the caches 2 and 3 change to the "clean" state. Upon completion of the write-back operation, a read access to the main memory 5 can be started in response to a request from the bus master 6.
Of the five cache states in response to a read request from the bus master 6 to the main memory 5, in cases (1) and (2), no write-back operation is performed on the CPU bus 7.
FIG. 3 is a timing chart showing an operation in cases (1) and (2) wherein no cache write-back operation is performed after a read request is output from a certain bus master 6 in the computer system having the conventional bus bridge shown in FIG. 2.
More specifically, when the bus master 6 gains control of the I/O bus 8 by a grant signal from the bus arbiter in response to an access request from the bus master 6 to the I/O bus 8 (timings t1 to t3), the bus master 6 supplies an address and a read command to the I/O bus control section 9 of the bus bridge 4 through the I/O bus 8 (timing t4).
The I/O bus control section 9 then outputs a cache snooping request signal "a" to the cache snooping section 10 (timing at t5). The cache snooping section 10 snoops the hit/miss and the dirty/clean state in the caches 2 and 3 through the CPU bus 7 (timings t6 to t9).
In this case, since no cache hit occurs, or data is clean even if a cache hit occurs, the cache snooping section 10 informs the I/O bus control section 9 by a cache snooping result signal "b" of the unnecessity of a cache write-back operation, i.e., permission to start a main memory read. The I/O bus control section 9 outputs a main memory read request signal "g" to the main memory control section 11 (timings t9 and t10).
Then, target data is read out from the main memory 5 in accordance with an address supplied from the bus master 6 to the main memory control section 11 through the I/O bus control section 9 (timings t10 to t14). The data read by the main memory control section 11 is supplied to the I/O bus control section 9 together with a main memory read end signal "h", and transferred to the bus master 6 through the I/O bus 8 (timings t14 and t15).
If no cache write-back operation is performed in response to a read request from the bus master 6 to the main memory 5, immediately after the unnecessity of a write-back operation is ascertained by snooping the caches, target data is read out from the main memory 5 and transferred to the bus master 6.
As the main memory 5, a DRAM is generally used. In accessing data corresponding to a target address in this DRAM, a row address is first supplied, and then a column address is supplied.
On the other hand, of the five cache states in response to a read request from the bus master 6 to the main memory 5, in cases (3) to (5), a write-back operation is performed on the CPU bus 7.
FIG. 4 is a timing chart showing an operation in cases (3) to (5) wherein a cache write-back operation is performed after a read request is output from the bus master 6 in the computer system having the conventional bus bridge shown in FIG. 2.
More specifically, when the bus master 6 gains control of the I/O bus 8 by a grant signal from the bus arbiter in response to an access request from the bus master 6 to the I/O bus 8 (timings t1 to t3), the bus master 6 supplies an address and a read command to the I/O bus control section 9 of the bus bridge 4 through the I/O bus 8 (timing t4).
A cache snooping request signal "a" is output from the I/O bus control section 9 to the cache snooping section 10 (timing at t5). The cache snooping section 10 snoops the hit/miss and the dirty/clean state in the caches 2 and 3 through the CPU bus 7 (timings t6 to t9).
In this case, since a cache hit occurs in the cache, and data is in the dirty state, the cache snooping section 10 informs the I/O bus control section 9 by a cache snooping result signal "b" of the necessity of a cache write-back operation. The I/O bus control section 9 is controlled to wait until write-back processing of write-back data in the main memory 5 is completed. At the same time, the cache snooping section 10 outputs a write-back processing request signal "c" to the write-back control section 12 (timing t9).
Then, the write-back control section 12 performs write-back processing for data corresponding to one cache line (e.g., 32-byte data; 64-bit data.times.4 times) with respect to the CPU bus 7 (timings t9 to t13). Subsequently, write-back processing for write-back data "DATA-X" with respect to the main memory 5 is performed in response to a main memory write-back request signal "d" from the write-back control section 12 to the main memory control section 11 (timings t13 to t19).
Upon completion of the write-back processing for the write-back data, the main memory control section 11 outputs a main memory write-back end signal "e" to the write-back control section 12. The write-back control section 12 outputs a write-back processing end signal "f" to the I/O bus control section 9 to inform it of permission to start a main memory read operation. The I/O bus control section 9 outputs a main memory read request signal "g" to the main memory control section 11 (timings t19 and t20).
Target data is read out from the main memory 5 in accordance with an address supplied from the bus master 6 to the main memory control section 11 through the I/O bus control section 9 (timings t20 to t24). The data read by the main memory control section 11 is supplied to the I/O bus control section 9 together with a main memory read end signal "h", and transferred to the bus master 6 through the I/O bus 8 (timings t24 and t25).
If a cache write-back operation is performed in response to a read request from the bus master 6 to the main memory 5, after the necessity of a write-back operation is determined by snooping the caches, write-back data is temporarily written back in the main memory 5, and then target data is read out from the main memory 5 and transferred to the bus master 6.
On the other hand, an operation performed when no cache write-back operation is performed in response to a write request from the bus master 6 is almost the same as the above-described operation (FIG. 3) performed when no cache write-back operation is performed in response to a read request, except that the command from the bus master 6 at timing t4 is a write command, the main memory access request signal "g" to the main memory control section 11 at timing t10 is replaced with a main memory write request signal, and data is written in accordance with the address supplied from the bus master 6 to the main memory control section 11 through the I/O bus control section 9.
If, therefore, no cache write-back operation is performed in response to a write request from the bus master 6 to the main memory 5, immediately after the unnecessity of a write-back operation is ascertained by snooping the caches, data from the bus master 6 is written in the main memory 5.
An operation performed when a cache write-back operation is performed in response to a write request from the bus master 6 is also almost the same as the above-described operation (FIG. 4) performed when a cache-write back operation is performed in response to a read request, except that the command from the bus master 6 at timing t4 is a write command, the main memory access request signal "g" to the main memory control section 11 at timing t20 is replaced with a main memory write request signal, and data is written in accordance with the address supplied from the bus master 6 to the main memory control section 11 through the I/O bus control section 9.
If a cache write-back operation is performed in response to a write request from the bus master 6 to the main memory 5, after the necessity of a write-back operation is established by snooping the caches, write-back data is temporarily written back in the main memory 5, and then data from the bus master 6 is written in the main memory 5.
In this manner, in the computer system using the conventional bus bridge (see FIG. 2), if no cache write-back operation is performed in response to an access request from the bus master 6 to the main memory 5, data can be immediately read out from or written in the main memory 5 in accordance with the address from the bus master 6. However, if a cache write-back operation is performed, data cannot be read out from or written in the main memory 5 until cache write-back data from the CPU bus 7 side is temporarily written back in the main memory 5. For this reason, to respond to a read/write request from the bus master 6, two stages of data processing must be performed for the main memory 5. Accordingly, as described above, as the frequency of write-back operations increases, i.e., the data sharing rate between the CPU 1 and the bus master 6 increases, the data read/write speed of the bus master 6 cannot be increased.